It is desirable to provide decoupling capacitance in a close proximity to an integrated circuit chip or die. The need for such capacitance increases as the switching speed and current requirements of chips or dies becomes higher. Thus, the need for a high number of passive components for high density integrated circuit chips or dies, the resultant increasing circuit density of printed wiring boards (PWB), and a trend to higher frequencies in the multi-gigaHertz range are among the factors combining to increase pressure on passive components surface-mounted on package substrates or PWBs. By incorporating embedded passive components (e.g., capacitors, resistors, inductors) into the package substrate or PWB, improved performance, better reliability, smaller footprint, and lower cost can be achieved.
Capacitors are the predominant passive component in most circuit designs. Typical materials for suitable embedded capacitor components, such as polymer and high-dielectric constant (high-k) ceramic powder composites or high-k ceramic powder and glass powder mixtures, are generally limited to a capacitance density on the order of nanoFarad/cm2 and 0.1 microFarad/cm2.
Creating thin films having a relatively large capacitance density, that is, a capacitance density greater or equal to one microFarad/cm2, on metal sheets that may serve as conductor material presents a number of challenges. One way to achieve large capacitance density would be to achieve a large dielectric constant, given that capacitance density and dielectric constant are directly proportional to one another. It is known that the dielectric constant of a material is, among other things, a function of the grain size of that material. In particular, as the grain size of a material increases, generally, so will its dielectric constant. However, growing thin films having large grain sizes, that is, thin films having grain sizes above about 50 nanometers (nm) to about 100 nm is a challenge. For example, growing a large grain microstructure requires an optimum combination of nucleation and grain growth. This is hard to achieve on a polycrystalline metal sheet. Typically, the multitude of random sites on a polycrystalline metal sheet act as nucleation sites, resulting in a microstructure with very small grain size (about 10 nm to about 50 nm). Once the film microstructure is composed of a large number of small grains, further heating will generally not result in a large grain microstructure, because a large number of similar-sized grains cannot grow into each other to form larger grains.
Attempts at creating thin films having a large capacitance density have shifted toward reducing a thickness of the deposited thin film dielectric, while avoiding the problems noted above with respect to creating dielectrics of large grain size. Thus, the prior art typically focuses on relatively small grain sized thin film technology (that is dielectric thin films having grain sizes in the range from about 10 nm to about 50 nm, with dielectric constants ranging from about 100 to about 450). To the extent that the capacitance density of a material is known to be inversely proportional to its thickness, the prior art has aimed at keeping the thickness of such dielectric films on the order of about 0.1 microns. However, disadvantageously, such films have tended to present serious shorting issues. First, a surface roughness of the metal sheet onto which the dielectric film has been deposited, to the extent that it is usually significant with respect to a thickness of the dielectric film, tends to present peaks and valleys into the dielectric film which in turn can lead to a direct shorting between the electrodes of a capacitor that includes the dielectric film. In addition, again, since a thickness of the dielectric film is small, voids typically present in the film will allow metal from at least one of the capacitor electrodes to seep into the voids, leading to shorting and leakage between the electrodes.
Voids in dielectric layers are disadvantageous for a number of other reasons. First, because of the presence of air pockets brought about as a result of the presence of voids, stress concentration points are typically created in the dielectric film, thus increasing the risk of crack propagation therein. In addition, to the extent that the dielectric constant of air is very small, the presence of air pockets results in a decrease in the overall dielectric constant of the dielectric layer. Thus, voids present disadvantages with respect to both the mechanical integrity and the electrical performance of a dielectric layer. The prior art proposes solving the problem of voids by exposing the dielectric layer to relatively long periods of sintering in order to densify the layer. However, such a solution disadvantageously increases the thermal budget required for the fabrication of a dielectric film, increasing cost while not necessarily guaranteeing a satisfactory reduction in the number of voids.